Reductions in sizes and inherent features of semiconductor devices have enabled continued improvements in speed, performance, density, and cost per unit function of integrated circuits over the past few decades. With the continuous scaling of integrated circuits, the conventional methods for improving performance of metal-oxide-semiconductor (MOS) devices, such as shortening gate lengths of MOS devices, has run into bottlenecks. To further enhance the performance of MOS devices, stress may be introduced in the channels of the MOS devices to improve carrier mobility. Generally, it is desirable to induce a tensile stress in the channel region of an n-type MOS (NMOS) device in a source-to-drain direction and to induce a compressive stress in the channel region of a p-type MOS (PMOS) device in a source-to-drain direction.
A commonly used method for applying compressive stress to the channel regions of PMOS devices is to grow SiGe stressors in source and drain regions. Such a method typically includes the steps of forming a gate stack on a semiconductor substrate; forming gate spacers on sidewalls of the gate stack; forming recesses in the silicon substrate along the gate spacers; epitaxially growing SiGe stressors in the recesses; and then annealing. Since SiGe has a greater lattice constant than silicon has, it applies a compressive stress to the channel region, which is located between a source SiGe stressor and a drain SiGe stressor. Similarly, for NMOS devices, stressors that may introduce tensile stresses, such as SiC stressors, may be formed.
The conventional stressor formation processes suffer drawbacks, however. FIG. 1 illustrates a conventional MOS device. A MOS device including source stressor 4 and drain stressor 6 are formed in substrate 2, wherein the bottom comers of source stressor 4 and drain stressor region 6 have a distance D. To increase the stress applied to the channel region, distance D is preferably small. Methods for forming stressors 4 and 6 closer to the channel region are thus explored. However, the decrease in distance D may result in a punch-through between source and drain regions, and a leakage current may flow between source and drain regions in path 8 below the channel region. This problem is further worsened due to the scaling down of integrated circuits, which causes distance D to further decrease.
What is needed in the art, therefore, is a novel MOS device that may take advantage of increased channel stress by reducing the distance between a source stressor and a drain stressor while at the same time overcoming the deficiencies of the prior art.